1. Field of the Invention
The present invention is related to sampler frequency converter circuits in general and in particular to a method and apparatus for increasing the frequency range, i.e. high frequency sensitivity response, of a sampler frequency converter in a vector network analyzer.
2. Description of the Prior Art
A vector network analyzer (VNA) is an analytical instrument used for measuring the electrical characteristics of a device-under-test (DUT). The VNA typically comprises a signal generator for generating test signals and a sampler frequency converter for sampling and down-converting the test signals which are transmitted through and/or reflected from the DUT.
A conventional sampler frequency converter comprises a sampling circuit having an input and an output, a step recovery diode (SRD) which provides pulses for controlling the sampling period of the sampling circuit, a local oscillator having a frequency F.sub.LO for driving the SRD and a filter.
In operation, reflected or transmitted input signals S.sub.IN having the frequency F.sub.IN received from a DUT are applied to the input of the sampling circuit. The local oscillator signals having the frequency F.sub.LO are applied to the SRD. In response thereto the SRD outputs pulses, i.e. sampling pulses, having a pulse repetition rate equal to the frequency of the output of the oscillator. These SRD sampling pulses are used to control the conduction period and the sampling rate of the sampling circuit. That is to say, the rate at which the sampling circuit samples the input signal S.sub.IN depends on the cycle time of the SRD sampling pulses and the period of each sample depends on the period of SRD sampling pulses.
A Fourier analysis of the sampling pulses from the SRD reveals that in the frequency domain the sampling pulses comprise a plurality of uniformly spaced spectral lines having a spacing corresponding to the pulse repetition rate of the pulses.
As the SRD sampling pulses sample the input signal S.sub.IN, the signal S.sub.IN having a frequency F.sub.IN is mixed with the spectral lines of the SRD pulses, producing an output signal S.sub.OUT having a frequency F.sub.OUT defined by the equation: EQU F.sub.OUT =.vertline.F.sub.IN .+-.N.times.F.sub.LO .vertline.(1)
where
N is the harmonic number 1, 2, 3 . . . For example, if the input signal S.sub.IN has a frequency F.sub.IN =1089 MHz and F.sub.LO =500 MHz, ##EQU1##
The bandpass filter described above is coupled to the output of the sampling circuit to pass a selected one of the spectral lines from S.sub.OUT. For example, if F.sub.IN =1089 MHz, F.sub.LO =500 MHz and the center frequency of the filter is 89 MHz, the 2nd harmonic of the output of the SRD at 1000 MHz will produce an 89 MHz signal on the output of the filter. Similarly, if F.sub.IN =59.589 GHz, the output of the filter will be produced in response to the 119th harmonic at 59 GHz.
In a sampler frequency converter as described above, as the frequency F.sub.IN of the input signal S.sub.IN is changed, the frequency F.sub.LO of the local oscillator is also changed so that the output of the filter remains centered at the center frequency of the bandpass filter. In addition, however, as the frequency F.sub.IN is increased, the insertion loss of the sampling circuit increases and thus, the amplitude of the output S.sub.OUT of the sampling circuit generally decreases according to the relationship (sin x)/x, where x=F.sub.IN, the frequency of the input signal S.sub.IN.
Heretofore, to increase the sampler frequency response of a given sampler as the frequency F.sub.IN of the input signal S.sub.IN was increased, it was the practice to reduce the sampler conduction period, i.e. sampling period. In practice, this was normally done by generating narrower SRD sampling pulses which had the net effect of moving the (sin x)/x response nulls higher in frequency. This practice, however, had the disadvantage that as the conduction duty cycle of the sampler was decreased, its output impedance was increased. Moreover, due to parasitic capacitance and other circuit limitations, further reductions in sampler conduction duty cycle were difficult to achieve in a practical circuit.